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FPGA design and DSP programming
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We analyzed the possibilities of developing a game machine with the resolution of 1600õ1200 pixels and the vertical-repetition frequency of 60Hz. |
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Audio interface converter based on FPGA Spartan-3E (XC3S250E) is implemented in
the media-player. Three I2S streams are separated from the data format packet
256 bit wide stream (generated by the Processor Blackfin ADSP-BF533 for AD1836)
for the subsequent transformation to S/PDIF. Multiplexed commutation between
incoming and outgoing streams is possible. The incoming I2S stream is forced for
the oversampling to 48 kHz. |
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The controller is designed for two video-streams composition purposes: first stream is from CMOS sensor, the second is artificial computer-generated."Frame-by-frame" editing algorithm is embedded with ability to generate the resulting output stream with a different video resolution and standard. Silica (AVNET) debugging boards, Texas Instruments 6416 DSK and user-defined video input daughterboard are implemented in the system. |
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The analyzer is intended for image analysis and processing. Three CMOS sensors are supplying data for subsequent 3D image reconstruction, according to a user-defined algorithm. AVNET (Silica) debugging boards and Texas Instruments 6416 DSK are applied for the controller. User-defined video input daughterboard has been developed for sensor`s connectivity. Micron MT9-SOC CMOS video-sensor with reading speed of 25 frames per second is used. |
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The module acquires data from CMOS sensor and controls its analogue inputs. Hardware IP cores and image preprocessing IP cores are developed. Interface with host CPU was realized. |
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The module is designed for reception, analysis and control of incoming data from various user transducers - up to 300 (weight, temperature, humidity, intensity of illumination, vibration, angularity, magnetic field and etc.). Memec (Avnet) debugging boards, user-defined daughterboard with DAC/ADC devices were applied for the controller implementation. |
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JV "Proscan Special Instruments" resorted to our service of "CPLD programming". We developed a number of IP core controllers, ISA, DMA, SDRAM, CMOS of the sensor Fillfactory LUPA-4000-M. On the basis of Xilinx picoBlaze CPU core and developed IP cores, we developed CSoC projects for HS-301F-1 and HS-301F-TEM cameras that were further mass produced by the client. |
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The controller is designed with ability to receipt, analyze and to distribute the user-defined UDP messages in Ethernet LAN. Two Memec (Avnet) debugging boards, user-defined daughterboard with six physical Ethernet PHY devices have been implemented in the present system. The system contains two Microblaze processor cores which exchange data via BRAM and one more Picoblaze processor core as an interrupt controller. The bundled messages are simultaneously receiving by six Ethernet controllers and forwarding for subsequent frames preprocessing, post-processing and future analysis. |
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A video system of two controlled high-resolution (1280x1024) video cameras and 16 controlled light sources was developed for a European customer specializing in optical control systems. For this project, custom boards to manage the video system were developed on the basis of EPLD by Xilinx. |
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Download PDF - 79Kb |
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