UFS IP Core
Ready-to-Use UFS IP Core for universal high performance storage interface
The UFS IP Core supports:
- JEDEC UFS 2.1
- MPHY version 3.0 type-1
- UniPro standard version 1.6
- PWM Gear-1 x 2-lane
- HS-Gear-1, HS-Gear-2, HS-Gear-3 x 2-lane via GTY
- AXI-Full and AXS interfaces
UFS IP core via GTY structure diagram
UFS IP via GTY consist of the next modules:
- UFS Low speed IP
- UFS High speed IP
- GTY control IP
- Mode control
- Write command FIFO
- Read command FIFO
- FIFO write data
- FIFO read data
- Status FIFO
- Register Map
UFS low speed IP structure diagram
Upgrade and Technical Support
Promwad provides free remote technical support for 1 year from the date of the IP core purchase. It includes consultation via phone, e-mail, and Skype. The maximum time for processing a request for technical support is 3 business days.
IMPORTANT NOTE: The overall free remote technical support will be limited to 60 hours. All over-limit hours will be charged on a T&M basis.
Extra Engineering Notes
The JESD220A UFS 2.1 specification defines a simple but high-performance serial interface that efficiently moves data between the host processor and storage devices. UFS IP uses the SCSI architecture model and command protocols that support multiple commands with command queuing capabilities, enabling multi-threaded programming.
To achieve high energy efficiency and performance in data transmission, UFS uses well-known interface standards for its interconnect layer:
- M-PHY – specification version 3.0
- UniPro – specification version 1.6
UniPro is a universal chip-to-chip protocol that provides a common channel for other protocols.
The M-PHY interface is the primary physical layer (PHY layer) for the UniPro specification and has a fast serial interface with up to 2.9 Gbps per lane (HS-G2), which can be scaled up to 5.8 Gbps per lane (HS-G3) using GTY PHY.
We can also customize our UFS IP for the LVDS PHY layer up to 1.2 Gbps per line (HS-G1) or other fast serial interfaces.
Our FPGA design projects
Would you like to use our IP core for your applications and embed UFS into your FPGA-based project?
Drop us a line about your project! We will contact you today or the next business day. All submitted information will be kept confidential.