ASIC Frontend Development
ASIC Validation and Prototyping Services
We help our clients to develop application-specific integrated circuits (ASICs) for their projects, focusing on the validation and prototyping phase, which goes after logical implementation.
If you're looking for a contractor for ASIC verification, testing, or driver development services, you have come to the right place. We have a qualified team with extensive experience in ASIC solutions.
Our services
This is the overview of ASIC design services we provide:
- Hardware blocks of simulation and validationon Zebu, HAPS or custom FPGA dev kitsÂ
- Testing with CPUs (i.e. RISC-V)Â
- ASIC emulation, virtual, hybrid (based on Zebu & HAPS)
- Hardware and software validation
- Software-based verification (ANSI C)
- Pre & post-silicon validation
- Custom divers development
- Pre silicon testing based on UVM
Featured Case-Study. Custom ASIC and FPGA Design
HAPS-80 Prototyping Solution by Synopsys
The project involved firmware development and testing for custom RISC-V-based ASIC.
Our team was involved in the following activities:
BSP and bare-metal drivers for RISC-V CPU development
Zero stage and first stage bootloaders
Windows driver for PCIe end-point device development (Jungo framework)
Implementing bring-up tests for all SoC components with communication over QSPI bridge
Simulation on ZeBu
Emulation on HAPS-80
Our team took part in the deployment of the concerned RTL design on the Xilinx Virtex US+ platform and interfacing with PHYs (Xilinx transceivers and external PHYs). We interfaced the following blocks designed by Synopsys:
PCIe root complexÂ
10G MAC and 10G PCSÂ
USB 3.0Â
The prototyping was implemented on VCU118 and HTG-960 evaluation kits with corresponding mezzanine cards. The simulation was launched on Vivado and VCS.
Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Kit
The peripheral components of the designed ASIC
PCIe end-point, AXI-DMA, GPIO, LPDDR4, UART
QSPI bridge
RISC-V
Watchdog timer, PVT sensor
Micro Case on ASIC Verification
Unpredictable impact deterministic detecting on CPU and parts
Tags: RISC-V, Test, Real-time determenistic
We designed and developed a library for real-time CPU internal tests. The test included internal and peripheral buses, internal CPU blocks, etc. The main idea is to immediately (deterministic time) detect any faults caused by any impact (including electromagnetic pulse).
We are boosting your ASIC development process by implementing C/ASM verification software for IP-blocks on Zebu, HAPS or other FPGA prototyping systems.
Our technology stack covers (but is not limited to) PCIe end-point, AXI-DMA, LPDDR4, QSPI, and RISC-V (SiFive). Feel free to contact us!
Are you interested in custom ASIC design for your projects?
Drop us a line about your project! We will contact you today or the next business day. All submitted information will be kept confidential.