FPGA Design
FPGA Design Development Services
FPGA design services at Promwad include firmware development for FPGA and MPSoC/RFSoC. We design and integrate IP cores, interface controllers, data processing algorithms, processor cores, and custom specialized modules.
Our team offers quality FPGA/MPSoC/RFSoC solutions for your project, according to the required budget, power consumption, and performance. We also create custom application-specific integrated circuits within our ASIC design services.
FPGA-Project at Promwad
As a FPGA design company, we perform the following activities:
- Specifications development.
- Architecture definition, selection of IP cores, including UFS IP cores.
- RTL descriptions development in VHDL/Verilog.
- DSP cores in Matlab Simulink (DSP – Digital signal processing).
- HLS — High-Level Synthesis. Logical and physical synthesis.
- Adaptation of IP cores to various FPGA families.
- FPGA based on AI-powered technologies.
Partnerships with the World Leading Vendors
We have permanent support from the leading FPGA vendors, including Xilinx, Lattice Semiconductor, Intel, and Microchip, to provide comprehensive embedded software development services.
Our FPGA, SoC, MPSoC Solutions
Explore the complete list of case studies categorized by vendors here.
Multi-electronic driver array and multi-electronic monitor array
Tags:Â Gowin, Xilinx, FPGA, USB 3.0, FTDI, PWM, ADC, Raspberry, Linux
- Multi-electronic driver array (MEDA) based on Xilinx Spartan-7Â by AMD: the unit sends the control signals to the programmable photonic integrated circuit. It programs the electrical power driving 128 channels connected to the programmable photonic integrated circuit.
- Multi-electronic monitor array (MEMA) based on Gowin GW1N: the unit reads the optical power monitors of the programmable photonic integrated circuit, closing the control loop. These monitors provide the information to compare the actual output with the expected one and update the MEDA's control signals.
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Bootloader development for the NX FPGA family
Tags: Lattice, RISC-V, bootloader, FPGA, Certus-NX, Сrosslink-NX
Development of a bootloader for the Lattice NX family with support for external QSPI flash memory. The project included hardware validation on dev boards based on Crosslink-NX and Сertus-NX. The SDRAM IP core can be adapted to the NX architecture and used with the RISC-V synthesizable core. Â
Firmware and software development of FPGA-based microscope
Tags:Â Zynq US+, Linux, Driver, SPI, XY2-100
Development of simple microscope firmware and software including signal generator for driving 2D scanners. Additional requirement was a software update opportunity for our customer's service, which is capable of updating the microscope firmware including the FPGA bit file. Signal generator provides automatic intermediate points generating using a second degree polynomial for analog channels.
Analog frontend real-time controller
Tags:Â Zynq US+, SDR, AGC, IQ, AFE
AGC, IQ imbalance compensation, and DC removal algorithms have been implemented in Zynq Ultrascale+/. The IP cores and software controls analog frontend board ICs provided parameters in real-time. AGC is table-based. IQ and DC techniques use surrogate optimization algorithm over ADC and mixer tunable parameters.Â
Unpredictable impact deterministic detecting on CPU and parts
Tags: RISC-V, Test, Real-time determenistic
We designed and developed a library for real-time CPU internal tests. The test included internal and peripheral buses, internal CPU blocks, etc. The main idea is to immediately (deterministic time) detect any faults caused by any impact (including electromagnetic pulse).
LVDS to MIPI CSI-2 video bridge with image processing
Tags: Artix7, Spartan7, CPU, MIPI CSI, LVDS, FTDI, Image processing, Image sensor
Cost-effective LVDS to MIPI CSI-2 video bridge with image processing:– input video resolution: 1920x1080 pixels– input framerate: 1000 fps– configurable MIPI CSI-2 parameters (default 1920x1080@30)– frame decimation or double buffering for reducing video stream data– configurable image processing parameters with FTDI interface
ADC/DAC repeater
Tags: Kintex Ultrascale, MicroTCA, JESD 204B, Linux, PCIe
We designed firmware for the MicroTCA system for buffering data from ADC in CPU x86 system and translating it to the DAC.– 1 Gsps ADC x8 channels– 2.8 Gsps DAC x8 channels– DMA– PCIe
Hybrid video capturing and processing device
Tags: Lattice, ECP5, HDMI, MIPI, H.265Â
Video stream capturing, h.265 compression, and streaming to the Internet. Lattice ECP5 used for video preprocessing and i.MX8 based SoM for compression, streaming, and user logic.
X-Ray sensors module
Tags: Lattice, ECP5, CMOSÂ
A small PCB module with 2xCMOS sensors and Lattice ECP5 for control and image processing.Â
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JESD204b data transfer to Linux
Tags: ZynqUS+, JESD204b, Llinux, ADC, DASÂ
A design for high-speed ADC and DAC capturing and streaming from/to PS DDR4 memory. The subsystem runs under Linux application control.
Printer controller
Tags: Xilinx, PCIe, Motor, Artix7
Custom solution for industrial printer motor control logic and raster image feeding.
Interface Extension FPGA project
Tags: Artix-7, MCU, ADC, SPI, I2C
Interface Extension FPGA project.
– big-endian and little-endian support for EMIF;
– direct access mode for MCU to end-points;
– auto mode for polling end-points in round-robin;
– arbiter switch for changing modes of access;
– ADC controller with daisy chain support and internal configurable median filter
Zynq US+ 1G ethernet
Tags: ZynqUS+, Networking, 1G, RPU, Cortex-r5, UDPÂ
An implementation of UDP protocol with hardware Gigabit ethernet controller (GEM). The data can be transmitted both from PL and PS subsystems.
– Hardware UDP offloader
– AXI4-Stream data interfaces
– Control driver for RPU
– Packets routing between PL and PS using IP portÂ
Zynq US+ 10G ethernet
Tags: ZynqUS+, Networking, 10G, UDPÂ
A hardware implementation of UDP protocol and 10G MAC.
– Hardware 10G UDP offloader
– AXI4-Stream data interfacesÂ
10G TCP/IP using Linux
Tags: ZynqUS+, Linux, 10G, TCP/IP, DDR4
The design solves the problem of reliable data transfer from PL to server. Data transferred directly from PS DDR4 via TCP/IP protocol. The achieved bandwidth is 3.5Gb over a 10G interface.
12G-SDI processing
Tags: Kintex7, Linux, PCI-E, SDI, Drivers
The design included in the Viewfinder product. Kintex-7 captures 12G-SDI signal, transmits video data to x86 CPU via PCIe. The Linux receives a video stream using a custom-designed V4L2 driver and outputs to the display.
4k HDMI frame buffer
Tags: Kintex7, Linux, PCI-E, HDMI, 4K, Drivers
– Linux driver for frame buffer
– Data transfer between x86 CPU and Kintex-7 via PCIe
– DDR3 for image buffering
– Two HDMI output interfaces
3G-SDI stream H.265 compression
Tags: Kintex7, Linux, PCI-e Jetson Nano, Drivers, H.265, SDIÂ
The device compresses a 3G-SDI input stream with the H.265 encoder. A V4L2 driver adapts the PCIe data stream to be processed by GStreamer and NVidia HW codec. Linux controls the output bitrate by network throughput estimation (QoS). The PCIe links and delivers a low latency encoding chain.
Advanced PCIe End-Point IP core
Tags: Kintex, Ultrascale, Artix7, Linux, PCI-e, Arria10, CycloneV
A multiplatform PCIe controller core wrapper providing up to 10 DMA channels and 6 BARs.
– Linux driver
– Kintex UltraScale / Artix7
– Arria10 / CycloneV
Nano seconds pulses processing
Tags: Kintex, Ultrascale+, Linux, MicroTCA, PCI-e, HLS, Simulink, JESD 204b
We designed firmware for the MicroTCA system for the statistical analysis of nanosecond pulses parameters.
– 2.7Gsps ADC x24 channels
– High-level synthesis tools for math
– Data aggregation by Linux
Radar data processing
Tags: Zynq Ultrascale+, Cortex-R5, ARM, lvds, 10g
We designed a PCB and firmware for the ADAR6901 radar data processing.
– Zynq UltraScale+
– Cortex-R5 for radar control
– Driver and HAL development
– High-speed LVDS interface
– DDR4 PL for data storage
– 10G interface for processed data downstreamingÂ
SoC firmware
Tags: SoC, RISC-V, FreeRTOS, Drivers, Bootloader
We’ve implemented firmware for a custom-designed SoC
– RISC-V CPU
– DesignWare IPs
– Bootloaders
– IPs bare-metal drivers
– Test environment
– User software
3G/12G SDI gearbox
Tags: Intel, Cyclone10, SDIÂ
A complete device has been designed for 3G and 12G signal processing. A custom Gearbox IP core for 4x3G<->12G streams conversion has been delivered with 2SI and SQD modes support.
Simple L2 switch IP core
Tags: Lattice, Ethernet
A single physical Ethernet port shared between the embedded CPU and MCU SoM. The stream is routed on the base of the device’s MAC addresses.Â
Video decoding and output to TFT panel
Tags: Lattice, H.264, H.265 MIPI, Display
A video TS stream decoded by an iMX8 SoM module. Transmitted to Lattice FPGA using MIPI CSI-2 interface and displayed on the TFT panel.
Image processing on ECP5
Tags: Lattice, Image Processing, HyperRam, Display
A video stream captured from HDMI interface. Then a chain of image processing operations takes place: white balance and gamma correction, cropping, scaling, and rotation. Finally, video displays on the TFT panel.
X-Ray imaging system
Tags: Lattice, CMOS, Xilinx, 1G
A complete device has been designed for image capturing from 80 X-Ray CMOS sensors. Image captured and pre-processed by Lattice MACHXO3, downstream to ARTIX7 motherboard as daisy-chain. FW update and other control operations mediated by external MCU.
Polarfire PCIe FMC carrier board
Tags: Microchip, Polarfire, FMC, PCI-e
We designed a high-end processing board with a PolarFire MPF500. Key features:
- 8 lanes of PCIe Gen2
- SPF+ cage
- FireFly x4
- Micro USB
- 16 GB DDR4
- FMC HPC connector
Polarfire mini-PCIe board
Tags: Microchip, Polarfire, Mini PCI-e
We designed a miniPCIe board with a Polarfire MPF300. Key features:
- IO connector with MGTs
- 4 GB DDR4
- PCIe x1, Gen 2
Polarfire mini-PCIe 3G-SDI card
Tags: Microchip, Polarfire, Mini PCI-e
We designed a miniPCIe 3G-SDI card with a PolarFire MPF300. Key features:
- 3G-SDI recording and playback
- 4 GB DDR4
- PCIe x1, Gen 2
BIOS emulation
Tags: Intel, HyperRAM, niosii, max10, qspi
MAX10+HyperRAM based BIOS emulator for secure Intel chipsets booting.
Multirate filter
Tags: Xilinx, Simulink, HDLcoder, Artix7
A multirate filter IP core has been generated from the Simulink model using HDL coder toolbox. Signal was buffered in the DDR3 memory for delay implementation.
Manufacturing testing equipment
Tags: Xilinx, ZynqUS+, MCU, tests
PCB and FW/SW for high-performance ZynqUS+ SoM modules tests at the manufacturing site.
Our Tech Map
Vitis/Vivado, Quartus Prime, Diamond, Libero, Matlab
NVidia Jetson, Alveo, OpenVINO, TensorFlow, Keras, Caffe
Verilog, VHDL, VivadoHLS, Simulink/HDL Coder, С/C++, Python
High-speed PCBs, DDR4, JESD204b, HDMI, SDI, SI, PI, Thermo modeling
Zynq US+, RFSoC, Cyclone10, ECP5, MPF500
AD9361, AD9371, ADRV9009, Radars, Custom AFE, Antenas
DPDK, UDP 10G, TCP 10G, TAPs, L1/L2 IP cores
1G, 10G, 25G/40G, 100G
"In case you are planning a project in complex data processing or high-speed throughput it’s the best way to choose FPGA programming. Our experts are ready to provide top-notch hardware design & firmware development services. Moreover, we are ready to give a hand with PCB & Schematic design – our experts have strong experience preparing projects of any complexity to mass manufacturing."
— Alex Krainov, CTO of Embedded Engineering
Our FPGA Design Projects
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