FPGA Projects
FPGA & SoC Project Library
Explore selected examples of our FPGA and SoC engineering work. Browse 30+ short case studies by silicon vendor, from 10G networking and JESD204B data capture to SDI video, radar processing and reusable IP cores.
Each entry shows the platform, the interfaces and what the design does. If you see a challenge close to yours, our engineers have already worked through similar architecture decisions — and can bring that experience to your project faster.
AMD ▪ Altera ▪ Lattice Semiconductor ▪ Microchip ▪ NVIDIA
AMD
ADC/DAC Repeater
Kintex® UltraScale™, MicroTCA, JESD204B, Linux, PCIe
We designed firmware for a MicroTCA system that buffers ADC data in an x86 CPU system and forwards it to the DAC.– 1 GSPS ADC, 8 channels– 2.8 GSPS DAC, 8 channels– DMA– PCIe
Analog Frontend Real-Time Controller
Zynq UltraScale+, SDR, AGC, IQ, AFE
We implemented AGC, IQ imbalance compensation, and DC offset removal algorithms on Zynq UltraScale+. The IP cores and software control the ICs on the analog front-end board in real time using the provided parameters. AGC is table-based. IQ and DC correction use a surrogate optimization algorithm over the tunable ADC and mixer parameters.
High-Speed Reliable Data Transfer over 4x10G
Zynq UltraScale+, DPDK, 10G, UDP, DDR4
We implemented a reliable data transfer chain from FPGA to server with an aggregate bandwidth of up to 38 Gbit/s. On the server side, the DPDK framework enables high-rate data reception. A custom protocol with retransmission ensures reliable delivery. Data is buffered in the external DDR4 memory attached to the PL.
Interface Extension FPGA Project
Artix™-7, MCU, ADC, SPI, I2C
– Big-endian and little-endian support for EMIF
– Direct access mode from the MCU to endpoints
– Automatic round-robin polling of endpoints
– Arbiter switch for changing access modes
– ADC controller with daisy-chain support and a configurable internal median filter
Zynq US+ 1G Ethernet
Zynq UltraScale+, Networking, 1G, RPU, Cortex-R5, UDP
An implementation of the UDP protocol using the hardware Gigabit Ethernet controller (GEM). Data can be transmitted from both the PL and PS subsystems.
– Hardware UDP offload engine
– AXI4-Stream data interfaces
– Control driver for the RPU
– Packet routing between PL and PS by IP port
Zynq UltraScale+ 10G Ethernet
Zynq UltraScale+, Networking, 10G, UDP
A hardware implementation of the UDP protocol and a 10G MAC.
– Hardware 10G UDP offload engine
– AXI4-Stream data interfaces
10G TCP/IP Using Linux
Zynq UltraScale+, Linux, 10G, TCP/IP, DDR4
The design provides reliable data transfer from the PL to a server. Data is sent directly from the PS DDR4 over TCP/IP, reaching a bandwidth of 3.5 Gbit/s over a 10G interface.
JESD204B Data Transfer to Linux
Zynq UltraScale+, JESD204B, Linux, ADC, DAC
A design for capturing and streaming high-speed ADC and DAC data from/to the PS DDR4 memory. The subsystem is controlled by a Linux application.
12G-SDI Processing
Kintex-7, Linux, PCIe, SDI, Drivers
This design is part of the Viewfinder product. A Kintex-7 FPGA captures the 12G-SDI signal and transmits the video data to an x86 CPU via PCIe. Linux receives the video stream through a custom V4L driver and outputs it to the display.
4K HDMI Frame Buffer
Kintex-7, Linux, PCIe, HDMI, 4K, Drivers
– Linux driver for frame buffer
– Data transfer between x86 CPU and Kintex-7 via PCIe
– DDR3 for image buffering
– Two HDMI output interfaces
Nanosecond Pulse Processing
Kintex-7, UltraScale+, Linux, MicroTCA, PCIe, HLS, Simulink, JESD204B
We designed firmware for a MicroTCA system that performs statistical analysis of nanosecond pulse parameters.
– 2.7 GSPS ADC, 24 channels
– High-level synthesis (HLS) for math functions
– Data aggregation under Linux
Radar Data Processing
Zynq UltraScale+, Cortex-R5, ARM, LVDS, 10G
We designed the PCB and firmware for processing radar data from the ADAR6901.
– Zynq UltraScale+
– Cortex-R5 for radar control
– Driver and HAL development
– High-speed LVDS interface
– DDR4 on the PL for data storage
– 10G interface for streaming processed data downstream
Multirate Filter
AMD, Simulink, HDL Coder, Artix-7
A multirate filter IP core was generated from a Simulink model using HDL Coder. The signal is buffered in DDR3 memory to implement the delay.
Printer Controller
AMD, PCIe, Motor, Artix-7
A custom solution for industrial printer motor control logic and raster image feeding.
Manufacturing Testing Equipment
AMD, Zynq UltraScale+, MCU, Testing
PCB and FW/SW for testing high-performance Zynq UltraScale+ SoM modules at the manufacturing site.
CoaXPress Frame Grabber Firmware
Zynq UltraScale+, CoaXPress
CoaXPress frame grabber firmware for a Zynq UltraScale+ MPSoC on a custom PCB, working with a Windows 10 host.
RFSoC ADC Data Capture
Zynq UltraScale+ RFSoC, ADC, SATA, SDR, I2C, SPI
We developed an ADC data capture system that captures data from 3 ADC channels, transfers it to the PS, and stores it on a SATA drive. The main challenge was transferring data from the PL to the PS without gaps. In addition to data capture, the Arm software configures the clocking subsystem via I2C/SPI.
Zynq UltraScale+ RFSoC is a single-chip adaptive radio platform.
Multichannel Driver & Monitor Arrays for Programmable Photonics
AMD, Spartan-7, Gowin GW1N, Photonics, PWM, TI DDC1128, FTDI FT601, USB 3.0, Raspberry Pi, Linux, Python, Closed-Loop Control
We developed two FPGA-based units that close the control loop of a programmable photonic integrated circuit. The driver array (MEDA) on an AMD Spartan-7 FPGA generates 128 independent PWM channels to control the electrical drive power applied to the chip.
The monitor array (MEMA) on a Gowin GW1N FPGA reads the chip’s optical power monitors through a 128-channel TI DDC1128 ADC and provides a programmable 0.5–5.0 V supply.
Both units connect to a Raspberry Pi 4 host over USB 3.0. A Python application on Linux compares the measured optical output with the expected one and updates the drive signals in real time.
FPGA Controller for a Nanosecond IR Laser
AMD, Zynq UltraScale+ MPSoC, Analog Devices, JESD204B, DSP, Closed-Loop Control, PROFINET, Hilscher netX 90, Laser Control, Industrial Automation
We developed an electronic controller for a nanosecond IR laser used to cut and drill metal and ceramics. Built on an AMD Zynq UltraScale+ MPSoC with an Analog Devices ADC/DAC front-end, it shapes every pulse in a closed loop: a waveform analyzer feeds correction data to the waveform generator in real time. The controller also manages the Q-switch, power supply, pump, and cooling, and connects to industrial PLCs over PROFINET.
- ADC/DAC sampling rate up to 3 GSPS
- Pulse repetition rate up to 100 kHz
- Pulse width down to 50 ns
- Closed-loop adaptive pulse shaping
- Integrated temperature control and HMI
Broadband SDR Satellite Modem Design
AMD, Zynq UltraScale+, SDR, Zero-IF, JESD204B, 4x10G, AGC, IQ Imbalance Compensation, Linux, REST/SNMP API
We designed a hardware and software platform for a satellite modem. This compact, scalable solution is built on a Zynq UltraScale+ platform with a custom front-end that uses high-speed converters and modulators/demodulators.
The final product covers a frequency range of 300 MHz to 2 GHz with bandwidth up to 500 MHz, and features a zero-IF architecture, multiple modulation formats, and error correction coding.
Multi-Beam Satellite Modem on RFSoC
AMD, Zynq UltraScale+ RFSoC, Multi-Beam, Star/Mesh Networks, L2/L3 Routing, PetaLinux, RTOS, DDR4, 1000BASE-X
We designed a next-generation satellite modem that supports various network configurations and advanced features.
The solution offers network flexibility, multi-beam capability, advanced waveforms (DVB-S2X, MF-TDMA), high data rates (40 Mbit/s per connection, 160 Mbit/s per network), and bridge/routing modes.
SDR Modem for Satellite Communication
AMD, Zynq UltraScale+ RFSoC DFE, SDR, RF ADC/DAC, Microchip VSC7440, L2/L3 Switching, SGMII, Gigabit Ethernet, 10G, DDR4, Redundant Power Supply
A high-performance software-defined radio (SDR) modem for satellite communication.
The modular design features a customizable analog front-end with LNAs, gain blocks, and filters, and supports up to 8 Gigabit Ethernet ports with optional 10G SFP+ connectivity. Redundant power supplies ensure reliable operation in critical communication applications.
Altera
Advanced PCIe End-Point IP Core
Kintex UltraScale, Artix-7, Linux, PCIe, Arria 10, Cyclone V
Multi-vendor IP: a multiplatform PCIe controller core wrapper providing up to 10 DMA channels and 6 BARs.
– Linux driver
– Kintex UltraScale / Artix-7
– Arria 10 / Cyclone V
3G/12G SDI Gearbox
Cyclone 10 GX, SDI
We designed a complete device for 3G and 12G signal processing, including a custom gearbox IP core for 4x3G ↔ 12G stream conversion with support for 2SI and SQD modes.
BIOS Emulation
Altera, HyperRAM, Nios II, MAX 10, QSPI
A BIOS emulator based on MAX 10 and HyperRAM for secure booting of Altera chipsets.
Lattice Semiconductor
Bootloader Development for NX FPGA Family
Lattice, RISC-V, bootloader, FPGA, Certus-NX, CrossLink-NX
We developed a bootloader for the Lattice NX FPGA family with support for external QSPI flash memory. The project included hardware validation on CrossLink-NX and Certus-NX development boards. The SDRAM IP core can be adapted to the NX architecture and used with the synthesizable RISC-V core.
Hybrid Video Capturing and Processing Device
Lattice, ECP5, HDMI, MIPI, H.265
Video stream capture, H.265 compression, and streaming to the internet. A Lattice ECP5 handles video preprocessing, while an i.MX8-based SoM handles compression, streaming, and application logic.
X-Ray Sensors Module
Lattice, ECP5, CMOS
A compact PCB module with two CMOS sensors and a Lattice ECP5 FPGA for control and image processing.
Simple L2 Switch IP Core
Lattice, Ethernet
A single physical Ethernet port is shared between the embedded CPU and the MCU SoM. Traffic is routed based on the devices’ MAC addresses.
Video Decoding and Output to TFT Panel
Lattice, H.264, H.265, MIPI, Display
An i.MX8 SoM decodes a video TS stream and transmits it to the Lattice FPGA over MIPI CSI-2 for output to a TFT panel.
Image Processing on ECP5
Lattice, Image Processing, HyperRAM, Display
A video stream is captured from the HDMI interface and passes through a chain of image processing operations: white balance and gamma correction, cropping, scaling, and rotation. The processed video is then displayed on the TFT panel.
X-Ray Imaging System
Lattice, CMOS, AMD, 1G
We designed a complete device that captures images from 80 X-ray CMOS sensors. A Lattice MachXO3 FPGA captures and preprocesses the images and passes them to an Artix-7 motherboard in a daisy chain. An external MCU handles firmware updates and other control operations.
Spherical Camera Systems
Lattice, CrossLink-NX, MIPI CSI-2, LVDS, DDR, I2C, SPI, CAN-FD, MCU, Image Processing
We designed a 360° camera monitoring system integrating four PAL/NTSC cameras. Each stream can be scaled, rotated, mirrored, and overlaid with markings.
Users can enable night mode with automatic illumination and adjust video parameters per stream. All configurations are saved for easy recall.
As a Lattice Certified Design Partner and FAE Service Partner, we help you choose the right device and bring it up fast.
Microchip
PolarFire Mini-PCIe Board
Microchip, PolarFire, Mini PCIe
We designed a miniPCIe board with a PolarFire MPF300 FPGA. Key features:
- IO connector with MGTs
- 4 GB DDR4
- PCIe x1, Gen 2
PolarFire PCIe FMC Carrier Board
Microchip, PolarFire, FMC, PCIe
We designed a high-end processing board with a PolarFire MPF500 FPGA. Key features:
- 8 lanes of PCIe Gen2
- SFP+ cage
- FireFly x4
- Micro USB
- 16 GB DDR4
- FMC HPC connector
PolarFire Mini-PCIe 3G-SDI Card
Microchip, PolarFire, Mini PCIe
We designed a miniPCIe 3G-SDI card with a PolarFire MPF300 FPGA. Key features:
- 3G-SDI recording and playback
- 4 GB DDR4
- PCIe x1, Gen 2
PolarFire SoM Module
Microchip, PolarFire, SoM
We designed a PolarFire MPF300 SoM module.
3G-SDI Video Capturing & Playback
Microchip, PolarFire, SDI
FPGA firmware, a host PC Linux driver, and an API for capturing and playing back 3G-SDI video streams.
NVIDIA
3G-SDI Stream H.265 Compression
Kintex-7, Linux, PCIe, Jetson Nano, Drivers, H.265, SDI
The device compresses a 3G-SDI input stream with an H.265 encoder. A V4L2 driver adapts the PCIe data stream for processing by GStreamer and the NVIDIA hardware codec. Linux controls the output bitrate based on estimated network throughput (QoS). The PCIe link enables a low-latency encoding chain.
Don’t See Your Exact Project Here?
Many of our projects are under NDA, so this library shows only part of our FPGA work. Tell us what you are building — an FPGA engineer will point out which proven building blocks we can reuse and where the real risks lie.