We developed a versatile framebuffer FPGA IP core and validated it on a custom Kintex-7 PC-e board and referencе Xilinx KC705 board.
FPGA implementations. It became a building block for PCI-e endpoint
We developed a versatile framebuffer FPGA IP core and validated it on a custom Kintex-7 PC-e board and referencе Xilinx KC705 board.
FPGA implementations. It became a building block for PCI-e endpoint

FPGA software development & Linux kernel drivers for 4K frame grabber

Challenge

A European company, specializing in the area of safety-critical systems for railway, transportation, and industrial applications turned to us for the development of FPGA software. The project consisted of two parts: framebuffer IP core development and PCI-e core development. 

 

Solution

1. Framebuffer IP core development

We developed a versatile framebuffer FPGA IP core and an appropriate Linux kernel framebuffer driver. Framebuffer IP core was validated on a custom Kintex-7 PCI-e board and reference Xilinx KC705 board.

The IP core supports:

  1. The ability to connect two monitors via two independent frame buffers;
  2. DVI, HDMI connection interfaces;
  3. PCIe Gen2 8x connection method to PCs;
  4. 16-bit high-color, 24-bit true-color;
  5. Resolutions:
  • 1920Ñ…1080
  • 1600Ñ…1200
  • 1920Ñ…1200
  • 3840Ñ…2160

 

2. PCI-e core development

Our engineers developed and integrated PCI-e IP core into the customer’s FPGA project. They validated it on Xilinx Artix 7, Xilinx UltraScale+, Intel Arria 10, Intel Cyclone 5 platforms.

PCI-e IP core features:

  • up to six BARs;
  • 4MB allocated size for each BAR;
  • 32-bit access to BARs;
  • up to 10 DMA channels with 1Gbit/sec throughput each;
  • legacy IRQ support;
  • configurable number for BARs and DMA channels.

 

Business value

The customer received the updated PCI-e graphics cards product line, which now supports modern monitors & indicating devices. Promwad FPGA team has successfully integrated PCI-e IP core into the customer's FPGA project. The developed IP core became a building block for PCI-e endpoint FPGA implementations and allowed further modifications to customer's requirements.

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