Ready-to-use IP Core Promwad


Ready-to-Use UFS IP Core for universal high performance storage interface

Promwad developed the UFS IP core as universal flash storage. UFS is widely used in mobile and other systems where large amounts of data must be stored, but standard RAM cannot be used, such as with camera solutions that have high resolution and data rates.

It provides a universal storage interface for both embedded and removable flash memory and is an ideal solution for applications that require high- performance and low power consumption. UFS IP is based on the MIPI M-PHY physical layer standard and uses MIPI Unipro as a link layer.

The UFS IP Core supports:

  • JEDEC UFS 2.1 
  • M-PHY version 3.0 type-1
  • UniPro standard version 1.6
  • PWM Gear-1 x 2-lane 
  • HS-Gear-1, HS-Gear-2, HS-Gear-3 x 2-lane via GTY 
  • AXI-Full and AXS interfaces
UFS IP core

UFS IP via GTY consists of the next modules:

  • UFS Low-speed IP
  • UFS High-speed IP
  • GTY control IP
  • Mode control
  • Switch
  • Write command FIFO
  • Read command FIFO
  • FIFO write data
  • FIFO read data
  • Status FIFO
  • Register Map
UFS IP core via GTY structure diagram

UFS IP core via GTY structure diagram

UFS low-speed IP structure diagram

UFS high-speed IP structure diagram
UFS IP core top view

Upgrade and Technical Support

Promwad provides free remote technical support for 1 year from the date of the IP core purchase. It includes consultations via phone, e-mail, and Skype. The maximum processing time for a technical support request is 3 business days.

IMPORTANT NOTE: The total free remote technical support is limited to 60 hours. Technical support time that goes over this limit will be charged on a T&M basis.



Extra Engineering Notes

The JESD220A UFS 2.1 specification defines a simple but high-performance serial interface that efficiently moves data between the host processor and storage devices. UFS IP uses the SCSI architecture model and command protocols that support multiple commands with command queuing capabilities, enabling multi-threaded programming.

To achieve high energy efficiency and performance in data transmission, UFS uses well-known interface standards for its interconnect layer:

  • M-PHY – specification version 3.0
  • UniPro – specification version 1.6

UniPro is a universal chip-to-chip protocol that provides a common channel for other protocols.

The M-PHY interface is the primary physical layer (PHY layer) for the UniPro specification and has a fast serial interface with up to 2.9 Gbps per lane (HS-G2), which can be scaled up to 5.8 Gbps per lane (HS-G3) using GTY PHY. 

We can also customize our UFS IP for the LVDS PHY layer up to 1.2 Gbps per line (HS-G1) or other fast serial interfaces.

Would you like to use our IP core for your applications and embed UFS into your FPGA-based project?

Drop us a line about your project! We will contact you today or the next business day. All submitted information will be kept confidential.