FPGA Programming services
Developing a cost-effective solution sometimes requires custom FPGA board programming due to a lack of necessary software or hardware capabilities.
We can define several reasons why FPGA programming is your best choice: power-consuming real-time algorithms, lack of required interfaces, or it is preferable to use hardware for some functions (especially in safety critical systems).
What are FPGAs?
FPGA stands for a field-programmable gate array and refers to a process of hardware customization on a single integrated circuit. FPGA boards can vary in form factors, programmable components number, memories, and purposes, but all serve to provide desirable flexibility.
FPGA-project at Promwad
Along with design services based on the solutions of global FPGA vendors, including Xilinx, Lattice Semiconductor, Intel, and Microchip, the Promwad Adaptive Computing Systems department performs the following activities:
- Specifications development.
- Architecture definition, selection of IP cores.
- RTL descriptions development in VHDL/Verilog.
- DSP cores in Matlab Simulink (DSP – Digital signal processing).
- HLS — High-Level Synthesis. Logical and physical synthesis.
- Adaptation of IP cores to various FPGA families.
- FPGA based on AI-powered technologies.
Fixed deadlines and budgets with an independent evaluation of your project. We are committed to your success and faster time to market.
Hundreds of completed projects in specific market segments with smooth-running processes, regular feedback and timely approval.
Flexible cooperation models tailored to your business goals and capacities. Let's discuss your goals and expectations.
Our key areas of expertise in FPGA programming
We illustrate our multi-field experience in FPGA programming:
Some of our FPGA, SoC, MPSoC solutions
Zynq US+ 10G ethernet
Tags: ZynqUS+, Networking, 10G, UDP
A hardware implementation of UDP protocol and 10G MAC.
– Hardware 10G UDP offloader
– AXI4-Stream data interfaces
10G TCP/IP using Linux
Tags: ZynqUS+, Linux, 10G, TCP/IP, DDR4
The design solves the problem of reliable data transfer from PL to server. Data transferred directly from PS DDR4 via TCP/IP protocol. The achieved bandwidth is 3.5Gb over a 10G interface.
4k HDMI frame buffer
Tags: Kintex7, Linux, PCI-E, HDMI, 4K, Drivers
– Linux driver for frame buffer
– Data transfer between x86 CPU and Kintex-7 via PCIe
– DDR3 for image buffering
– Two HDMI output interfaces
3G-SDI stream H.265 compression
Tags: Kintex7, Linux, PCI-e Jetson Nano, Drivers, H.265, SDI
The device compresses a 3G-SDI input stream with the H.265 encoder. A V4L2 driver adapts the PCIe data stream to be processed by GStreamer and NVidia HW codec. Linux controls the output bitrate by network throughput estimation (QoS). The PCIe links and delivers a low latency encoding chain.
Advanced PCIe End-Point IP core
Tags: Kintex, Ultrascale, Artix7, Linux, PCI-e, Arria10, CycloneV
A multiplatform PCIe controller core wrapper providing up to 10 DMA channels and 6 BARs.
– Linux driver
– Kintex UltraScale / Artix7
– Arria10 / CycloneV
Nano seconds pulses processing
Tags: Kintex, Ultrascale+, Linux, MicroTCA, PCI-e, HLS, Simulink, JESD 204b
We designed firmware for the MicroTCA system for the statistical analysis of nanosecond pulses parameters.
– 2.7Gsps ADC x24 channels
– High-level synthesis tools for math
– Data aggregation by Linux
Radar data processing
Tags: Zynq Ultrascale+, Cortex-R5, ARM, lvds, 10g
We designed a PCB and firmware for the ADAR6901 radar data processing.
– Zynq UltraScale+
– Cortex-R5 for radar control
– Driver and HAL development
– High-speed LVDS interface
– DDR4 PL for data storage
– 10G interface for processed data downstreaming
Tags: sov, RISC-V, FreeRTOS, Drivers, Bootloader
We’ve implemented firmware for a custom-designed SoC
– RISC-V CPU
– DesignWare IPs
– IPs bare-metal drivers
– Test environment
– User software
Video decoding and output to TFT panel
Tags: Lattice, H.264, H.265 MIPI, Display
A video TS stream decoded by an iMX8 SoM module. Transmitted to Lattice FPGA using MIPI CSI-2 interface and displayed on the TFT panel.
Image processing on ECP5
Tags: Lattice, Image Processing, HyperRam, Display
A video stream captured from HDMI interface. Then a chain of image processing operations takes place: white balance and gamma correction, cropping, scaling, and rotation. Finally, video displays on the TFT panel.
Our tech map in FPGA
Vitis AI, Vivado Design Suite, Quartus Prime, SDAccel, SDSoC, HDL Coder
Xilinx Deep Neural Network (xDNN), Alveo, OpenVINO, TensorFlow, Keras, Caffe
Tools & Languages
C++, Python, Matlab/Simulink, Verilog, VHDL, HLS, DSP, AI toolboxes
High-speed interfaces, DDR4, JESD204b, SI, PI, Thermo modeling, Video processing
Zynq, Zynq US+, RF SoC, Xilinx Versal, FPGA
AD9361, AD9371, ADRV9009, Radars, Promwad AFE, Antenas
DPDK, UDP 10G, TCP 10G, TAPs, L1/L2 IP cores
PCI-e, 1G, 10G, 25G/40G, 100G
Our FPGA programming projects
Do you need a quote for your FPGA programming project?
Drop us a line about your project! We will contact you today or the next business day. All submitted information will be kept confidential.