FPGA Design
FPGA Design Services
FPGA design services at Promwad implies firmware development for FPGA and MPSoC/RFSoC. We design and integrate IP cores, interface controllers, data processing algorithms, processor cores, and custom specialized modules.
Our engineering team offers the best choice of FPGA/MPSoC/RFSoC for your project, according to the required budget, power consumption, and performance.
FPGA-project at Promwad
FPGA-project service at Promwad involves the following activities:
- Specifications development.
- Architecture definition, selection of IP cores.
- RTL descriptions development in VHDL/Verilog.
- DSP cores in Matlab Simulink (DSP – Digital signal processing).
- HLS — High-Level Synthesis. Logical and physical synthesis.
- Adaptation of IP cores to various FPGA families.
- FPGA based on AI-powered technologies.
Partnership with the world leading vendors
We have permanent support from the leading FPGA vendors: Xilinx, Lattice Semiconductor, Intel, and Microchip.
Our FPGA, SoC, MPSoC solutions
Explore the complete list of case studies categorized by vendors here.
Zynq US+ 1G ethernet
Tags: ZynqUS+, Networking, 1G, RPU, Cortex-r5, UDP
An implementation of UDP protocol with hardware Gigabit ethernet controller (GEM). The data can be transmitted both from PL and PS subsystems.
– Hardware UDP offloader
– AXI4-Stream data interfaces
– Control driver for RPU
– Packets routing between PL and PS using IP port
Zynq US+ 10G ethernet
Tags: ZynqUS+, Networking, 10G, UDP
A hardware implementation of UDP protocol and 10G MAC.
– Hardware 10G UDP offloader
– AXI4-Stream data interfaces
10G TCP/IP using Linux
Tags: ZynqUS+, Linux, 10G, TCP/IP, DDR4
The design solves the problem of reliable data transfer from PL to server. Data transferred directly from PS DDR4 via TCP/IP protocol. The achieved bandwidth is 3.5Gb over a 10G interface.
JESD204b data transfer to Linux
Tags: ZynqUS+, JESD204b, Llinux, ADC, DAS
A design for high-speed ADC and DAC capturing and streaming from/to PS DDR4 memory. The subsystem runs under Linux application control.
12G-SDI processing
Tags: Kintex7, Linux, PCI-E, SDI, Drivers
The design included in the Viewfinder product. Kintex-7 FPGA captures 12G-SDI signal, transmits video data to x86 CPU via PCIe. The Linux receives a video stream using a custom-designed V4L driver and outputs to the display.
4k HDMI frame buffer
Tags: Kintex7, Linux, PCI-E, HDMI, 4K, Drivers
– Linux driver for frame buffer
– Data transfer between x86 CPU and Kintex-7 via PCIe
– DDR3 for image buffering
– Two HDMI output interfaces
3G-SDI stream H.265 compression
Tags: Kintex7, Linux, PCI-e Jetson Nano, Drivers, H.265, SDI
The device compresses a 3G-SDI input stream with the H.265 encoder. A V4L2 driver adapts the PCIe data stream to be processed by GStreamer and NVidia HW codec. Linux controls the output bitrate by network throughput estimation (QoS). The PCIe links and delivers a low latency encoding chain.
Advanced PCIe End-Point IP core
Tags: Kintex, Ultrascale, Artix7, Linux, PCI-e, Arria10, CycloneV
A multiplatform PCIe controller core wrapper providing up to 10 DMA channels and 6 BARs.
– Linux driver
– Kintex UltraScale / Artix7
– Arria10 / CycloneV
Nano seconds pulses processing
Tags: Kintex, Ultrascale+, Linux, MicroTCA, PCI-e, HLS, Simulink, JESD 204b
We designed firmware for the MicroTCA system for the statistical analysis of nanosecond pulses parameters.
– 2.7Gsps ADC x24 channels
– High-level synthesis tools for math
– Data aggregation by Linux
Radar data processing
Tags: Zynq Ultrascale+, Cortex-R5, ARM, lvds, 10g
We designed a PCB and firmware for the ADAR6901 radar data processing.
– Zynq UltraScale+
– Cortex-R5 for radar control
– Driver and HAL development
– High-speed LVDS interface
– DDR4 PL for data storage
– 10G interface for processed data downstreaming
SoC firmware
Tags: sov, RISC-V, FreeRTOS, Drivers, Bootloader
We’ve implemented firmware for a custom-designed SoC
– RISC-V CPU
– DesignWare IPs
– Bootloaders
– IPs bare-metal drivers
– Test environment
– User software
3G/12G SDI gearbox
Tags: Intel, Cyclone10, SDI
A complete device has been designed for 3G and 12G signal processing. A custom Gearbox IP core for 4x3G<->12G streams conversion has been delivered with 2SI and SQD modes support.
Simple L2 switch IP core
Tags: Lattice, Ethernet
A single physical Ethernet port shared between the embedded CPU and MCU SoM. The stream is routed on the base of the device’s MAC addresses.
Video decoding and output to TFT panel
Tags: Lattice, H.264, H.265 MIPI, Display
A video TS stream decoded by an iMX8 SoM module. Transmitted to Lattice FPGA using MIPI CSI-2 interface and displayed on the TFT panel.
Image processing on ECP5
Tags: Lattice, Image Processing, HyperRam, Display
A video stream captured from HDMI interface. Then a chain of image processing operations takes place: white balance and gamma correction, cropping, scaling, and rotation. Finally, video displays on the TFT panel.
X-Ray imaging system
Tags: Lattice, CMOS, Xilinx, 1G
A complete device has been designed for image capturing from 80 X-Ray CMOS sensors. Image captured and pre-processed by Lattice MACHXO3 FPGA, downstream to ARTIX7 motherboard as daisy-chain. FW update and other control operations mediated by external MCU.
Polarfire PCIe FMC carrier board
Tags: Microchip, Polarfire, FMC, PCI-e
We designed a high-end processing board with a PolarFire MPF500 FPGA. Key features:
- 8 lanes of PCIe Gen2
- SPF+ cage
- FireFly x4
- Micro USB
- 16 GB DDR4
- FMC HPC connector
Polarfire mini-PCIe board
Tags: Microchip, Polarfire, Mini PCI-e
We designed a miniPCIe board with a Polarfire MPF300 FPGA. Key features:
- IO connector with MGTs
- 4 GB DDR4
- PCIe x1, Gen 2
Polarfire mini-PCIe 3G-SDI card
Tags: Microchip, Polarfire, Mini PCI-e
We designed a miniPCIe 3G-SDI card with a PolarFire MPF300 FPGA. Key features:
- 3G-SDI recording and playback
- 4 GB DDR4
- PCIe x1, Gen 2
BIOS emulation
Tags: Intel, HyperRAM, niosii, max10, qspi
MAX10+HyperRAM based BIOS emulator for secure Intel chipsets booting.
Multirate filter
Tags: Xilinx, Simulink, HDLcoder, Artix7
A multirate filter IP core has been generated from the Simulink model using HDL coder toolbox. Signal was buffered in the DDR3 memory for delay implementation.
Printer controller
Tags: Xilinx, PCIe, Motor, Artix7
Custom solution for industrial printer motor control logic and raster image feeding.
Manufacturing testing equipment
Tags: Xilinx, ZynqUS+, MCU, tests
PCB and FW/SW for high-performance ZynqUS+ SoM modules tests at the manufacturing site.
Our tech map in FPGA
Vitis/Vivado, Quartus Prime, Diamond, Libero, Matlab
NVidia Jetson, Alveo, OpenVINO, TensorFlow, Keras, Caffe
Verilog, VHDL, VivadoHLS, Simulink/HDL Coder, С/C++, Python
High-speed PCBs, DDR4, JESD204b, HDMI, SDI, SI, PI, Thermo modeling
Zynq US+, RFSoC, Cyclone10, ECP5, MPF500
AD9361, AD9371, ADRV9009, Radars, Custom AFE, Antenas
DPDK, UDP 10G, TCP 10G, TAPs, L1/L2 IP cores
1G, 10G, 25G/40G, 100G
"In case you are planning a project in complex data processing or high-speed throughput it’s the best way to choose FPGA programming. Our experts are ready to provide top-notch hardware design & firmware development services. Moreover, we are ready to give a hand with PCB & Schematic design – our experts have strong experience preparing projects of any complexity to mass manufacturing."
— Alex, the head of the Adaptive Computing Systems department at Promwad
Our FPGA design projects
Do you need a quote for your FPGA design project?
Drop us a line about your project! We will contact you today or the next business day. All submitted information will be kept confidential.